1. Field of the Invention
Generally, the present disclosure generally relates to the manufacturing of sophisticated semiconductor devices, and, more specifically, to various methods of making transistor devices with elevated source/drain regions to accommodate consumption of silicon during metal silicide formation process.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein field effect transistors (NMOS and PMOS transistors) represent one important type of circuit element used in manufacturing such integrated circuit devices. A field effect transistor, irrespective of whether an NMOS transistor or a PMOS transistor is considered, typically comprises doped source and drain regions that are formed in a semiconducting substrate that are separated by a channel region. A gate insulation layer is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region.
Device designers are under constant pressure to increase the operating speed and electrical performance of transistors and integrated circuit products that employ such transistors. Given that the gate length (the distance between the source and drain regions) on modern transistor devices may be approximately 30-50 nm, and that further scaling is anticipated in the future, device designers have employed a variety of techniques in an effort to improve device performance, e.g., the use of high-k dielectrics, the use metal gate electrode structures, the incorporation of work function metals in the gate electrode structure and the use of channel stress engineering techniques on transistors (create a tensile stress in the channel region for NMOS transistors and create a compressive stress in the channel region for PMOS transistors). Stress engineering techniques typically involve the formation of specifically made silicon nitride layers that are selectively formed above appropriate transistors, i.e., a layer of silicon nitride that is intended to impart a tensile stress in the channel region of a NMOS transistor would only be formed above the NMOS transistors. Such selective formation may be accomplished by masking the PMOS transistors and then blanket depositing the layer of silicon nitride, or by initially blanket depositing the layer of silicon nitride across the entire substrate and then performing an etching process to selectively remove the silicon nitride from above the PMOS transistors. Conversely, for PMOS transistors, a layer of silicon nitride that is intended to impart a compressive stress in the channel region of a PMOS transistor is formed above the PMOS transistors. The techniques employed in forming such nitride layers with the desired tensile or compressive stress are well known to those skilled in the art. Since the stress-inducing layers are removed from the final device, the stress in the final device is believed to be a “memorized” or residual stress that present in the gate electrode and/or the source/drain regions of the device.
In a field effect transistor, metal silicide regions are typically formed in the source/drain regions of a transistor to reduce the resistance when a conductive contact is formed to establish electrical connection to the source/drain regions. The metal silicide regions are typically formed after a desired stress level has been established for a transistor using the aforementioned stress-inducing silicon nitride layers. Such metal silicide regions may be made using a variety of different refractory metals, e.g., nickel, platinum, cobalt, etc., and they may be formed using techniques that are well known to those skilled in the art. The typical steps performed to form metal silicide regions are: (1) depositing a layer of refractory metal on an exposed surface of a silicon-containing material, such as exposed source/drain regions; (2) performing an initial heating process that causes the refractory metal to react with underlying silicon-containing material; (3) performing an etching process to remove unreacted portions of the layer of refractory metal and (4) performing an additional heating process to form the final phase of the metal silicide.
The formation of metal silicide regions on source/drain regions consumes some of the silicon material—some of the stressed source/drain material near the surface of the substrate. For example, forming a metal silicide region having a final thickness of about 30 nm, consumes about 25 nm of the underlying silicon material. Removal of the stressed source/drain material eliminates some of the desired stress established for the transistor. This is particularly problematic because the silicidation process consumes portions of the source/drain region that are near the level of the conductive channel region that will be established under the gate insulation layer when the transistor is “turned on.”
The present disclosure is directed to various methods of forming source/drain regions that may solve or at least reduce one or more of the problems identified above.